1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device and a control method thereof, and more particularly to a NOR flash memory with a metal oxide nitride oxide semiconductor (MONOS) structure.
2. Description of the Related Art
Recently, in a NOR flash memory, it becomes more difficult to shrink the gate length as the generation proceeds. This is because it is necessary to apply a drain voltage (write voltage) of 3 eV or more in order for carriers to jump over an energy barrier of a silicon oxide film (tunnel oxide film) lying between a charge storage layer and a channel in a NOR flash memory of a channel hot electron (CHE) injection system. However, as the gate length of a memory cell (the gate electrode of a cell transistor) is shrunk, the punch-through withstand voltage between the drain and the source is lowered. If the punch-through withstand voltage becomes lower than the write voltage required for writing, an erroneous write phenomenon occurs.
The erroneous write phenomenon is a phenomenon in which the threshold voltage of a non-selected cell varies at the write time. That is, if the gate length is excessively reduced, the withstand voltage cannot be maintained and a leak current occurs when a write voltage of 3V, which is the same as that applied to a selected cell or more, is applied to the drain terminal of a non-selected cell commonly connected to a write bit line. Then, electrons or holes caused by an unintentional channel current that flows through the drain-source path act on the gate electrode and change the threshold voltage of the non-selected cell.
As the flash memory of the CHE injection system, an alternate conversion virtual ground (alternate metal virtual ground: AMG) flash memory is already known (for example, see 1997 Symposium On VLSI Technology Digest of Technical Papers pp. 67-68 “A NEW FLASH ARCHITECTURE WITH A 5.8λ2 SCALABLE AMG FLASH CELL”, Anirban R., et al). The AMG flash memory is a flash memory of a CHE injection system having floating gates, but it can be replaced by a trap flash memory with a MONOS structure having no floating gates.
However, in the trap flash memory with the MONOS structure, the following problem occurs. That is, since a plane structure in which the gate electrodes are formed above the silicon substrate is provided, the rate of shrink of memory cells is controlled according to the gate lengths thereof when the punch-through withstand voltage between the drain and the source is lowered.